1. Field of the Invention
The present invention relates to processors having embedded memories and more particularly to exposing and debugging defects within embedded memories of processors.
2. Description of the Related Art
Digital systems include data paths, control paths and memories. Many known digital systems, such as microprocessors, include embedded memories. One challenge associated with embedded memories relates to identifying defects within the embedded memory. Defects in memories may be due to shorts and opens in memory cells of the embedded memories, address decoder(s) and read/write logic. These defects may be modeled as Stuck-at Faults (SAF), Transition Faults (TF), Stuck Open Faults (SOF), Address Decoder Faults (AF), Coupling Faults (CF) and Neighborhood Pattern Sensitive Faults (NPSF) in the memory cells.
Pluralities of classes of test algorithms have been proposed for detection of the memory faults. The pluralities of classes of test algorithms include deterministic test algorithms, pseudo random test algorithms and pseudo exhaustive test algorithms. A known deterministic test algorithm is a march test algorithm. A march test algorithm involves applying a finite sequence of march elements to each cell in the memory in either ascending or descending order before proceeding to the next memory cell. Different types of march tests are used to detect faults in single-port memories and recently in multi-port memories have been proposed.
The memory test algorithms can be applied to the memory under test via memory testers. Testing via a memory tester involves providing a test bus from the input/output pins of the memory to the boundary of the integrated circuit in which the memory is embedded. Testing via a memory tester has known drawbacks including the wiring overhead of the test bus to access the memory under test and the cost of memory testers. Advantages of testing via a memory tester include the level of controllability and observability on the memory under test and the fact that the memory under test is tested at speed or at the speed that the I/O can allow it. To overcome the wiring overhead, serial-to-parallel interfaces have been included within an integrated circuit in which memory is embedded. Thus, the test bus is reduced in width; however, the delay for serial-to-parallel conversion becomes a bottle neck for at speed memory test.
A typical high performance microprocessor has approximately 100-150 embedded memories. Considering complexity of these devices and the fact that the Input/Output (I/O) connections are much slower than their core clock rate, the external tester method is often an ineffective and inefficient method to test the memories embedded within large scale integrated circuits such as microprocessors.
A known method for testing embedded memories is by providing an embedded memory built in self test (MBIST) module to apply memory test patterns to the embedded memories. An MBIST module includes different components including a memory BIST controller. The memory BIST controller realizes the memory test algorithm. Known memory BIST controllers have been designed as Finite State Machine (FSM) based controllers or as microcode-based controllers. The FSM based memory BIST controller is efficient but lacks the flexibility necessary to accommodate changes in a memory test algorithm. The ability to change the memory test algorithm is desirable for devices fabricated using new technologies as well as debugging a field return part. Microcode-based controllers are flexible and can apply different test algorithms. However, the efficiency and effectiveness of a microcode based controller depends on the architecture of the controller.
Regardless of the capabilities of the memory BIST module, it is desirable for the memory BIST module to be activated and for test algorithm to be customized in different levels of test, e.g., manufacturing-level, board-level and system-level test. This implies that the memory BIST module should be able to communicate with different interfaces using different protocols. Furthermore, the status of the test should be made available and should be readily extractable.
Known embedded memories undergo different levels of test during the course of their design and fabrication. For example, a memory BIST is activated and run as a part of manufacturing-level, board-level and system-level tests. Often each level of test requires a different type of interface and protocol. For example, during a manufacturing level test, the pins of the chip are accessible and used to communicate with the memory BIST while during a system level test, a service processor access is used to communicate to the memory BIST.
It is desirable to provide a memory BIST with complete communication interface with an activation interface, a status interface and a customization interface. However, depending on the size of the integrated circuit in which the memory BIST is embedded and the number of the memories that are tested via the memory BIST and because it is desirable for the memory BIST module to be placed close to the memories under test, the cost associated with creating this communication interface for each instantiation of a memory BIST module in a design with high number of embedded memories is high. A memory BIST architecture that provides an efficient communication interface would result in lower area overhead and easier verification.